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10-Bit Integrated, Multiformat SDTV/HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface
ADV7441A
FEATURES
Multiformat decoder Four 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels SCART fast blank sampling support NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan formats support 720p-/1080i-/1080p-component HD formats support Digitizes RGB graphics from VGA to UXGA rates (up to 1600 x 1200 @ 60 Hz) VBI data slicer (including teletext) Analog-to-HDMI fast switching mode Dual High-Definition Multimedia Interface (HDMI) Rx 2:1 multiplexed HDMI receiver HDMI 1.3, DVI 1.0 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) 36-bit deep color support S/PDIF (IEC60958-compatible) digital audio output Multichannel I2S audio output (up to 8 channels) Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM General Highly flexible output interface STDI function support standard identification 2 any-to-any 3 x 3 color-space conversion matrices Programmable interrupt request output pins
GENERAL DESCRIPTION
The ADV7441A is a high quality multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed HDMITM receiver. The ADV7441A contains two main processing sections. The first section is the standard definition processor (SDP), which processes all types of PAL, NTSC, and SECAM signals. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7441A can keep the HDCP link between a HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes. As a decoder, the ADV7441A can convert PAL, NTSC, and SECAM composite or S-Video signals into a digital ITU-R BT.656 format. It can also decode a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards as well as many other HD and SMPTE standards. SCART and overlay functionality are enabled by the ability of the ADV7441A to process CVBS and standard definition RGB signals simultaneously. As a graphics digitizer, the ADV7441A can digitize RGB graphics signals from VGA to UXGA rates and convert them to a digital RGB or YCrCb pixel output stream. The ADV7441A incorporates a dual-input HDMI 1.3-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA. The reception of encrypted video is possible with the inclusion of HDCP. The inclusion of adaptive equalization in the HDMI receiver ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, including a mute controller that prevents audible extraneous noise in the audio output. To facilitate professional applications, where HDCP processing and decryption is not required, a derivative part of the ADV7441A is available. This allows users who are not HDCP adopters to purchase the ADV7441A. See the Ordering Guide for details. Fabricated using an advanced CMOS process, the ADV7441A is available in a space-saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the -40C to +85C temperature range.
APPLICATIONS
Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP(R) rear projection HDTVs CRT HDTVs LCoS(R) HDTVs Audio/video receivers (AVR) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2008 Analog Devices, Inc. All rights reserved.
ADV7441A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Electrical Characteristics ............................................................. 4 Video Specifications ..................................................................... 6 Analog and HDMI Specifications .............................................. 7 Timing Characteristics ................................................................ 8 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 Thermal Resistance .................................................................... 10 Package Thermal Performance ................................................. 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Functional Overview ...................................................................... 14 Analog Front End ....................................................................... 14 HDMI Receiver ........................................................................... 14 Standard Definition Processor Pixel Data Output Modes .... 14 Component Processor Pixel Data Output Modes.................. 14 Composite and S-Video Processing ......................................... 14 Component Video Processing .................................................. 15 RGB Graphics Processing ......................................................... 15 General Features ......................................................................... 15 Theory of Operation ...................................................................... 16 Analog Front End ....................................................................... 16 HDMI Receiver........................................................................... 16 Standard Definition Processor ................................................. 16 Component Processor (CP) ...................................................... 17 VBI Data Processor .................................................................... 17 Pixel Output Formatting................................................................ 18 Register Map Architecture ........................................................ 22 Typical Connection Diagram ....................................................... 23 Recommended External Loop Filter Components ................ 24 AD9388A/ADV7441A Evaluation Platform .............................. 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26
REVISION HISTORY
7/08--Rev. SpA to Rev. B 5/08--Rev. Sp0 to Rev. SpA Changes to General Description Section ...................................... 1 Change to Clamp Level (When Locked) Parameter, Table 3 ...... 7 Changes to Standard Definition Processor Pixel Data Output Modes Section ................................................................................. 14 Changes to Component Processor Pixel Data Output Modes Section ................................................................................. 14 Changes to Table 8 .......................................................................... 18 Added Table 9.................................................................................. 18 Added Table 10 ............................................................................... 19 Added Table 11 ............................................................................... 20 Added AD9388A/ADV7441A Evaluation System Section ....... 25 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 10/07--Revision Sp0: Initial Version
Rev. B | Page 2 of 28
VBI DATA PROCESSOR VBI DECODER ANCILLARY DATA FORMATTER ANCILLARY DATA
ANALOG INTERFACE ADC0 DATA PROCESSOR EMBEDDED SYNC SYNC SOURCE AND POLARITY DETECT STANDARD IDENTIFICATION AV CODE INSERTION 10 OFFSET ADDRESS MACROVISION(R) AND CGMS DETECTION PROGRAM DELAY DIGITIAL FINE CLAMP GAIN CONTROL SYNC EXTRACT 10 CHA COMPONENT PROCESSOR
DIGITAL PROCESSING BLOCK
CVBS 10 CHB
CLAMP
RGB ADC1 10
CLAMP
INPUT MATRIX ADC2
YPrPb
CLAMP
PIXEL DATA P0 TO P9 10
FUNCTIONAL BLOCK DIAGRAM
YC AND CVBS HS/CS, VS CONTROL CONTROL C Y NOISE AND CALIBRATION DECIMATION AND DOWNSAMPLING FILTERS
CLAMP ADC3
10
CHC COLOR SPACE CONVERTER CHA CHD CHB CHC
P10 TO P19 10
SOG SOY HS_IN/CS_IN VS_IN
LLC GENERATION
ACTIVE PEAK AND HSYNC DEPTH
P20 TO P29
SYNC PROCESSING AND CLOCK GENERATION
MUX
Figure 1.
CONTROL AND DATA CONTROL FILTER SYNC EXTRACT LUMA DIGITAL FINE CLAMP LUMA FILTER FSC RECOVERY
STANDARD DEFINITION PROCESSOR
OUTPUT FORMATTER
G B R FB
FB
RXA_C
4:2:2 TO 4:4:4 CONVERSION
MUX
HDMI DECODE
DATA RECOVERY ALIGNMENT
RXB_C HS
CHROMA DIGITAL FINE CLAMP
RXB_0
RXB_1
SAMPLER
VBI DATA RECOVERY
GLOBAL CONTROL MACROVISION DETECTION STANDARD AUTODETECTION
SYNTHESIZED LLC CONTROL FREE RUN OUTPUT CONTROL
EQUALIZER MUX EQUALIZER
HDCP ENGINE
EDID/REPEATER CONTROLLER
HDCP EEPROM
MDA MCL
PACKET PROCESSOR
RXB_2
DDCA_SCL DDCA_SDA DDCB_SDA DDCB_SCL
06914-001
ADV7441A
PACKET/ INFOFRAME MEMORY
AUDIO PROCESSING
I2S LRCLK SCLK MCLKOUT SPDIF
FAST BLANK OVERLAY CONTROL
PLL VS
XOR
Rev. B | Page 3 of 28
DE CHROMA DEMOD CHROMA FILTER
SCL SDA
GAIN CONTROL
LUMA RESAMPLE
LUMA 2D COMB (0x04 MAX)
INT1
ALSB
CONTROL INTERFACE I2C
LINE LENGTH PREDICTOR
RESAMPLE CONTROL
AV CODE INSERTION
HS/CS VS/FIELD DE/FIELD CTI C-DNR
RXA_0
RXA_1
SAMPLER
RXA_2
LLC GAIN CONTROL CHROMA RESAMPLE CHROMA 2D COMB (0x04 MAX) SFL/ SYNC_OUT/ INT2
ADV7441A SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 1.
Parameter 1 STATIC PERFORMANCE 2 Resolution (Each ADC) Integral Nonlinearity Symbol N INL Test Conditions Min Typ Max 10 -4/+6 Unit Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB V V V V A A pF V V A pF V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA
Differential Nonlinearity
DNL
BSL 27 MHz (@ a 10-bit level) BSL 54 MHz (@ a 10-bit level) BSL 74 MHz (@ a 10-bit level) BSL 110 MHz (@ a 10-bit level) BSL 170 MHz (@ an 8-bit level) At 27 MHz (@ a 10-bit level) At 54 MHz (@ a 10-bit level) At 74 MHz (@ a 10-bit level) At 110 MHz (@ a 10-bit level) At 170 MHz (@ an 8-bit level) 2 0.7
-0.5/+2 -0.5/+2 -0.5/+1.5 -0.7/+2 -0.25/+0.5 -0.5/+0.5 0.5 0.5 0.5 -0.25/+0.2
-0.95/+2
DIGITAL INPUTS Input High Voltage 3 Input Low Voltage3 Input Current Input Capacitance 4 DIGITAL OUTPUTS Output High Voltage 5 Output Low Voltage5 High Impedance Leakage Current Output Capacitance4 POWER REQUIREMENTS4 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current
VIH HS_IN/CS_IN, VS_IN low trigger mode VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD TVDD CVDD IDVDD ISOURCE = 0.4 mA ISINK = 3.2 mA HS_IN/CS_IN, VS_IN low trigger mode Pin 21 (RESET) All input pins other than Pin 21
-60 -10
0.8 0.3 +60 +10 10
2.4 0.4 10 20 1.62 2.97 1.71 1.71 3.135 1.71 1.8 3.3 1.8 1.8 3.3 1.8 140 141 152 203 242 242 16 17 16 42 17 20 1.98 3.63 1.89 1.89 3.465 1.89 189 252 205 263 329 326 48 37 50 61 34 34
Digital I/O Supply Current
IDVDDIO
CVBS input sampling @ 54 MHz 6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz 7, 8 HDMI RGB sampling @ 225 MHz7, 8 CVBS input sampling @ 54 MHz6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8
Rev. B | Page 4 of 28
ADV7441A
Parameter 1 HDMI Comparators TMDS PLL and Equalizer Supply Current Symbol ICVDD Test Conditions CVBS input sampling @ 54 MHz6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 CVBS input sampling @ 54 MHz6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 CVBS input sampling @ 54 MHz6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8, 10 HDMI RGB sampling @ 225 MHz7, 8, 10 CVBS input sampling @ 54 MHz6 Graphics RGB sampling @ 108 MHz6 SCART RGB fast blank sampling @ 54 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 Min Typ 56 56 56 56 86 95 63 174 225 180 0 0 12 12 12 12 42 63 18 14 17 19 10 15 11.6 25 Max 78 78 79 79 105 118 102 278 348 284 2 2 18 18 18 18 47 69 23 21 23 24 19 20 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ms
Analog Supply Current 9
IAVDD
Terminator Supply Current
ITVDD
Audio and Video PLL Supply Current
IPVDD
Power-Down Current Power-Up Time
1 2 3
IPWRDN tPWRUP
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). All ADC linearity tests were performed at input range full scale - 12.5% and at zero scale + 12.5%. Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant. 4 Guaranteed by characterization. 5 The VOH and VOL levels were obtained using the default drive strength value (0x15) in User Map Register 0xF4. 6 Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA, Bit 7 programmed with Value 0) and with no HDMI sources connected to the part. 7 Current measurements for HDMI inputs were made with a source connected to the active HDMI port and with no source connected to the inactive HDMI port. 8 Audio stream is a noncompressed stereo audio sampling frequency of fS = 48 kHz, and MCLKOUT = 256 fS. 9 Analog current measurements for CVBS were made with only ADC0 powered up; for RGB, with only ADC0, ADC1, and ADC2 powered up; for SCART FB, with all ADCs powered up; and for HDMI mode, with all ADCs powered off. 10 The terminator supply current may vary with the HDMI source in use.
Rev. B | Page 5 of 28
ADV7441A
VIDEO SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 2.
Parameter 1, 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range FSC Subcarrier Lock Range Color Lock-In Time Synchronization Depth Range 3 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy
1 2 3
Symbol DP DG LNL
Test Conditions CVBS input, modulated in five steps CVBS input, modulated in five steps CVBS input, five steps Luma ramp Luma flat field
Min
Typ 0.3 0.6 0.8 61.8 63.1 60
Max
Unit Degrees % % dB dB dB
-5 40 1.3 60 20 5 2 100 HUE CL_AC 5 0.5 0.1 0.3 CVBS, 0.5 V input CVBS, 0.5 V input 1 1 1 1
+5 70
200 200
% Hz kHz Lines % % Fields Lines Degrees % % % Degrees % % %
400
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. Nominal synchronization depth is 300 mV at 100% of the synchronization depth range.
Rev. B | Page 6 of 28
ADV7441A
ANALOG AND HDMI SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 3.
Parameter 1, 2 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance (Except Pin 74) Input Impedance of Pin 74 Common-Mode Level (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Test Conditions Min Typ 0.1 10 20 0.88 CML + 0.5 CML - 0.5 1 CML - 0.122 CML - 0.167 CML- 0.122 CML CML - 0.120 CML CML CML - 0.120 8 8 0.25 0.4 0.4 0.2 tpixel 5 + 1.78 ns Max Unit F M k V V V V V V V V V V V V mA mA A A tbit 4
Clamps switched off
Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current HDMI SPECIFICATIONS 3 Intrapair (Positive-to-Negative) Differential Input Skew Channel-to-Channel Differential Input Skew
1 2
CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y signal) Component input (Pr signal) Component input (Pb signal) PC RGB input (R, G, B signals) SDP only SDP only SDP only SDP only
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. 3 Guaranteed by design. 4 tbit is 1/10 the pixel period tpixel. 5 tpixel is the period of the TMDS clock.
Rev. B | Page 7 of 28
ADV7441A
TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 4.
Parameter 1, 2 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORTS (FAST MODE) 3 xCL Frequency 4 xCL Minimum Pulse Width High4 xCL Minimum Pulse Width Low4 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time4 xCL and xDA Rise Times4 xCL and xDA Fall Times4 Setup Time for Stop Condition I2C PORTS (NORMAL MODE)3 xCL Frequency4 xCL Minimum Pulse Width High4 xCL Minimum Pulse Width Low4 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time4 xCL and xDA Rise Times4 xCL and xDA Fall Times4 Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (SDP) 5 Data Output Transition Time SDR (CP) 6 I2S PORT (MASTER MODE) SCLK Mark Space Ratio LRCLK Data Transition Time I2Sx Data Transition Time 7 MCLKOUT Frequency
1 2
Symbol
Test Conditions
Min
Typ 28.6363
Max
Unit MHz ppm kHz MHz kHz s s s s ns ns ns s kHz s s s s ns ns ns s ms
14.8 12.825
50 110 170 400
t1 t2 t3 t4 t5 t6 t7 t8
0.6 1.3 0.6 0.6 100 300 300 0.6 100
t1 t2 t3 t4 t5 t6 t7 t8
4 4.7 4 4.7 250 1000 300 4 5
t9:t10 t11 t12 t13 t14 t15:t16 t17 t18 t19 t20 Negative clock edge to start of valid data End of valid data to negative clock edge End of valid data to negative clock edge Negative clock edge to start of valid data
45:55
55:45 3.4 2.4 2 0.5
% duty cycle ns ns ns ns % duty cycle ns ns ns ns MHz
45:55 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 4.096
55:45 10 10 5 5 24.576
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. 3 Refers to all I2C pins (DDC and control port). 4 The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S. 5 SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4. 6 CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4. 7 The suffix x refers to pin names ending with 0, 1, 2, and 3.
Rev. B | Page 8 of 28
ADV7441A
TIMING DIAGRAMS
t3
xDA
t5
t3
t6
xCL
t1
NOTES 1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.
Figure 2. I2C Timing
t9
LLC
t10
t11 t12
06914-003
P0 TO P29, VS, HS, DE/FIELD, SFL/SYNC_OUT
Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)
t9
t10
LLC
t13 t14
P0 TO P29, VS, HS, DE/FIELD
06914-004
Figure 4. Pixel Port and Control SDR Output Timing (CP Core)
t15
SCLK
t16 t17
LRCLK
t18
I2Sx LEFT-JUSTIFIED MODE
t19
MSB MSB - 1
t20
I2Sx I2S MODE I2Sx RIGHT-JUSTIFIED MODE MSB
t19
MSB - 1
t20
MSB
t19
LSB
06914-007
NOTES 1. THE SUFFIX x REFERS TO PIN NAMES ENDING WITH 0, 1, 2, AND 3.
t20
Figure 5. I2S Timing
Rev. B | Page 9 of 28
06914-002
t2
t7
t4
t8
ADV7441A ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD to AGND DVDD to DGND PVDD to PGND DVDDIO to DGND CVDD to CGND TVDD to TGND DVDDIO to AVDD DVDDIO to TVDD DVDDIO to DVDD CVDD to DVDD PVDD to DVDD AVDD to CVDD AVDD to PVDD AVDD to DVDD AVDD to TVDD TVDD to DVDD Digital Inputs Voltage to DGND Digital Outputs Voltage to DGND Analog Inputs Voltage to AGND Maximum Junction Temperature (TJ_MAX) Storage Temperature Range Infrared Reflow, Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 4V 2.2 V 4V -0.3 V to +3.6 V -3.6 V to +3.6 V -2 V to +2 V -2 V to +0.3 V -2 V to +0.3 V -2 V to +2 V -2 V to +2 V -2 V to +0.3 V -3.6 V to +0.3 V -2 V to +2 V DGND - 0.3 V to DVDDIO + 0.3 V DGND - 0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 125C -65C to +150C 260C
THERMAL RESISTANCE
Table 6.
Package Type 144-Lead LQFP (ST-144)
1
JT1 1.62
Unit C/W
Junction-to-package surface thermal resistance.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption during ADV7441A operation, turn off unused ADCs. On a four-layer PCB that includes a solid ground plane, the value of JA is 25.3C/W. However, due to variations within the PCB metal and, therefore, variations in PCB heat conductivity, the value of JA may differ for various PCBs. The most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature, because this is not affected by the variance associated with the value of JA. The maximum junction temperature (TJ_MAX) of 125C must not be exceeded. The following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on DUT: TJ_MAX = TS + (JT x WTOTAL) where: TS is the surface temperature of the package expressed in degrees Celsius. JT is the junction-to-package surface thermal resistance. WTOTAL = {(AVDD x IAVDD) + (DVDD x IDVDD) + (DVDDIO x IDVDDIO) + (PVDD x IPVDD) + (CVDD x ICVDD) + (TVDD x ITVDD)}. Contact an Analog Devices, Inc., sales representative or send an e-mail to video.products@analog.com for more information on package thermal performance.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. B | Page 10 of 28
ADV7441A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
DDCB_SDA SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP SDA SCL ALSB DGND DVDDIO DE/FIELD HS/CS VS/FIELD INT1 SFL/SYNC_OUT/INT2 RESET DGND DVDD P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 DGND DVDDIO P10
DDCB_SCL DGND DVDD CVDD CGND TVDD RXB_2P RXB_2N TGND RXB_1P RXB_1N TGND RXB_0P RXB_0N TGND RXB_CP RXB_CN TVDD CGND CVDD RTERM TVDD RXA_2P RXA_2N TGND RXA_1P RXA_1N TGND RXA_0P RXA_0N TGND RXA_CP RXA_CN TVDD CGND CVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PIN 1
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
ADV7441A
TOP VIEW (Not to Scale)
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TEST5 TEST4 DDCA_SDA DDCA_SCL CVDD CGND AUDIO_ELPF PVDD PGND AIN6 AIN12 SOY AIN5 AIN11 AIN4 AIN10 REFP TEST3 REFN TEST2 AVDD AGND CML REFOUT AVDD AGND AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG FB TEST0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 EXT_CLK DGND DVDDIO LLC P22 P23 P24 P25 DGND DVDD P26 P27 P28 P29 VS_IN HS_IN/CS_IN DGND XTAL1 XTAL DVDDIO PVDD PGND ELPF PVDD PGND
72
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 14, 22, 34, 49, 56, 64, 143 82, 83, 87 69, 72, 100 103, 110, 126, 140 114, 117, 120, 130, 133, 136 15, 35, 50, 67 23, 57, 142 84, 88 68, 71, 101 104, 109, 125, 141 111, 123, 127, 139 74 73, 91, 108 89 Mnemonic DGND AGND PGND CGND TGND DVDDIO DVDD AVDD PVDD CVDD TVDD FB TEST0, TEST3, TEST5 TEST2 Type 1 G G G G G P P P P P P I I O Description Digital Ground. Analog Ground. PLL Ground. Comparator Ground. Terminator Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Audio and Video PLL Supply Voltage (1.8 V). HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). Terminator Supply Voltage (3.3 V). Fast Blank. Fast switch overlay between CVBS and RGB analog signals. Test Pins. Do not connect. Test Pin. Do not connect.
Rev. B | Page 11 of 28
06914-005
ADV7441A
Pin No. 107 76 to 81, 93 to 96, 98, 99 24 to 33, 36 to 47, 52 to 55, 58 to 61 19 20 Mnemonic TEST4 AIN1 to AIN12 P0 to P29 INT1 SFL/SYNC_OUT/INT2 Type 1 I/O I O O O Description Test Pin. Do not connect. Analog Video Input Channels. Video Pixel Output Port. Interrupt Signal. Can be active low or active high. The set of events that triggers an interrupt is under user control. Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode. Interrupt Signal (INT2). Horizontal Synchronization Output Signal (HS). Output by the SDP and CP. Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses. Vertical Synchronization Output Signal (VS). Output by the SDP and CP. Field Synchronization Output Signal (FIELD). Field synchronization output signal in all interlaced video modes. Data Enable Signal (DE). Indicates active pixel data. Field Synchronization Output Signal (FIELD). Field synchronization output signal in all interlaced video modes. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for the control port. This pin sets the second LSB of the slave address for each ADV7441A register map. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7441A circuitry. Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In crystal mode, the crystal must be a fundamental crystal. Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the ADV7441A. The recommended external loop filter must be connected to this ELPF pin. The recommended external loop filter must be connected to this AUDIO_ELPF pin. Internal Voltage Reference Output. Common-Mode Level for the Internal ADCs. Internal Voltage Reference Output. Internal Voltage Reference Output. HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 series resistor is recommended on the HS_IN/CS_IN pin. VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance, a 100 series resistor is recommended on the VS_IN pin. Synchronization-on-Green Input. This pin is used in embedded synchronization mode. Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface.
Rev. B | Page 12 of 28
17
HS/CS
O
18
VS/FIELD
O
16
DE/FIELD
O
11 12 13 21 51 65
SDA SCL ALSB RESET LLC XTAL1
I/O I I I O O
66 70 102 85 86 90 92 63
XTAL ELPF AUDIO_ELPF REFOUT CML REFN REFP HS_IN/CS_IN
I O O O O O O I
62 75 97 112 113 115 116 118 119 121 122
VS_IN SOG SOY RXA_CN RXA_CP RXA_0N RXA_0P RXA_1N RXA_1P RXA_2N RXA_2P
I I I I I I I I I I I
ADV7441A
Pin No. 128 129 131 132 134 135 137 138 106 1 105 144 2 3 4 5 6 7 8 9 10 48 124
1
Mnemonic RXB_CN RXB_CP RXB_0N RXB_0P RXB_1N RXB_1P RXB_2N RXB_2P DDCA_SDA DDCB_SDA DDCA_SCL DDCB_SCL SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP EXT_CLK RTERM
Type 1 I I I I I I I I I/O I/O I I O O O O O O O O I I I
Description Digital Input Clock Complement of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. HDCP Slave Serial Data Port A. HDCP Slave Serial Data Port B. HDCP Slave Serial Clock Port A. HDCP Slave Serial Clock Port B. SPDIF Digital Audio Output. I2S Audio (Channel 1 and Channel 2). I2S Audio (Channel 3 and Channel 4). I2S Audio (Channel 5 and Channel 6). I2S Audio (Channel 7 and Channel 8). Data Output Clock for Left and Right Audio Channels. Audio Serial Clock Output. Audio Master Clock Output. External Clamp Signal Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. Sets internal termination resistance. Connect this pin to TGND using a 500 resistor.
G = ground, P = power, I = input, O = output.
Rev. B | Page 13 of 28
ADV7441A FUNCTIONAL OVERVIEW
The following overview provides a brief description of the functionality of the ADV7441A. More details are available in the Theory of Operation section.
COMPOSITE AND S-VIDEO PROCESSING
The ADV7441A supports NTSC (M/J/4.43), PAL (B/D/I/G/H/ M/N/Nc/60), and SECAM (B/D/G/K/L) standards for CVBS and S-Video formats. Superadaptive 2D, 5-line comb filters for NTSC and PAL provide superior chrominance and luminance separation for composite video. The composite and S-Video processing functionality also includes fully automatic detection of switching among worldwide standards (PAL/NTSC/SECAM); automatic gain control (AGC) with white peak mode to ensure that the video is processed without compromising the video processing range; Adaptive Digital Line Length Tracking (ADLLTTM); and proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners. The IF filter block compensates for high frequency luma attenuation due to the tuner SAW filter. Other features include chroma transient improvement (CTI); luminance digital noise reduction (DNR); color controls for hue, brightness, saturation, contrast; Cr and Cb offset controls; certified Macrovision copy protection detection on composite and S-Video for all worldwide formats (PAL/NTSC/SECAM); 4x oversampling (54 MHz) for CVBS, S-Video, and YUV modes; line-locked clock output (LLC); support for letterbox detection; a free-run output mode for stable timing when no video input is present; a vertical blanking interval data processor; teletext; a video programming system (VPS); vertical interval time codes (VITC); closed captioning (CC) and extended data service (EDS); wide-screen signaling (WSS); a copy generation management system (CGMS); clocking from a single 28.63636 MHz crystal; and subcarrier frequency lock (SFL) output for downstream video encoders. The differential gain of the ADV7441A is 0.6% typical, and differential phase is 0.3 typical.
ANALOG FRONT END
The analog front end of the ADV7441A provides four high quality 10-bit ADCs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. SCART functionality and standard definition RGB overlay with CVBS are controlled by the FB input.
HDMI RECEIVER
The ADV7441A is compatible with the HDMI 1.3 specification. The ADV7441A supports all HDTV formats up to 1080p and all display resolutions up to UXGA (1600 x 1200 @ 60 Hz). The device includes the following features: * * * * Adaptive front-end equalization for HDMI operation with cable lengths up to 30 meters. Synchronization conditioning for higher performance in strenuous conditions. Audio mute for removing extraneous noise. Programmable data island packet interrupt generator.
STANDARD DEFINITION PROCESSOR PIXEL DATA OUTPUT MODES
The ADV7441A features the following SDP output modes: * * * 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD. 16-/20-bit YCrCb 4:2:2 with embedded time codes and/or HS, VS, and FIELD. 24-/30-bit YCrCb 4:4:4 with embedded time codes and/or HS, VS, and FIELD.
COMPONENT PROCESSOR PIXEL DATA OUTPUT MODES
The ADV7441A features single data rate outputs as follows: * * * 8-/10-bit 4:2:2 YCrCb for 525i and 625i. 16-/20-bit 4:2:2 YCrCb for all standards. 24-/30-bit 4:4:4 YCrCb/RGB for all standards.
Rev. B | Page 14 of 28
ADV7441A
COMPONENT VIDEO PROCESSING
The ADV7441A supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats; automatic adjustments for gain (contrast) and offset (brightness); manual adjustment controls; analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, and CS; and YCrCb-to-RGB and RGB-to-YCrCb conversions by any-toany, 3 x 3, color-space conversion matrices. In addition, the ADV7441A features brightness, saturation, and hue controls. Standard identification (STDI) enables detection of the component format at the system level, and a synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video. Certified Macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p). When no video input is present, free-run output mode provides stable timing. The ADV7441A supports user-defined pixel sampling for nonstandard video sources and arbitrary pixel sampling for nonstandard video sources.
RGB GRAPHICS PROCESSING
The ADV7441A provides 170 MSPS conversion rate support of RGB input resolutions up to 1600 x 1200 @ 60 Hz (UXGA) and automatic or manual clamp and gain controls for graphics models. The RGB graphics processing functionality features contrast and brightness controls, automatic detection of synchronization source and polarity by the SSPD block, standard identification enabled by the STDI block, and user-defined pixel sampling support for nonstandard video sources. Additional RGB graphics processing features of the ADV7441A include the following: * * * * Sampling PLL clock with 500 ps p-p jitter at 170 MSPS. 32-phase DLL support of optimum pixel clock sampling. Color-space conversion of RGB to YCrCb and decimation to a 4:2:2 format for videocentric back-end IC interfacing. Data enable (DE) output signal supplied for direct connection to the HDMI/DVI transmitter IC.
GENERAL FEATURES
The ADV7441A features HS, VS, and FIELD output signals with programmable position, polarity, and width; and programmable interrupt request output pins, INT1 and INT2. The part also offers low power consumption: 1.8 V digital core, 1.8 V analog, and 3.3 V digital input/output and low power powerdown mode. The ADV7441A operates over a temperature range of -40C to +85C and is available in a 144-lead, 20 mm x 20 mm, RoHScompliant LQFP.
Rev. B | Page 15 of 28
ADV7441A THEORY OF OPERATION
ANALOG FRONT END
The ADV7441A analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP. The analog front end uses differential channels connected to each ADC to ensure high performance in mixed-signal applications. The analog front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7441A. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in either the CP or SDP. The ADCs are configured to run in 4x oversampling mode when decoding composite and S-Video inputs. For component 525i, 625i, 525p, and 625p sources, 2x oversampling is performed, but 4x oversampling is available for component 525i and 625i. All other video standards are 1x oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing (AA) filters with the benefit of an increased signalto-noise ratio (SNR). The ADV7441A supports simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output, as controlled by the I2C registers and the FB pin. The HDMI receiver also offers advanced audio functionality. The receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops.
STANDARD DEFINITION PROCESSOR
The SDP section is capable of decoding a large selection of baseband video signals in composite, S-Video, and YUV formats. The video standards supported by the SDP include PAL (B/D/I/G/H/60/M/N/Nc), NTSC (M/J/4.43), and SECAM (B/D/G/K/L). The ADV7441A automatically detects the video standard and processes it accordingly. The SDP has a 5-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7441A implements the patented ADLLT algorithm to track varying video line lengths from sources such as VCRs. ADLLT enables the ADV7441A to track and decode poor quality video sources, such as VCRs, and noisy sources, such as tuner outputs, VCD players, and camcorders. The SDP also contains a CTI processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as teletext, closed captioning (CC), wide-screen signaling (WSS), a video programming system (VPS), vertical interval time codes (VITC), a copy generation management system (CGMS), and an extended data service (XDS). The ADV7441A SDP section has a Macrovision 7.1 detection circuit that allows it to detect Type I, Type II, and Type III protection levels. The decoder is fully robust to all Macrovision signal inputs.
HDMI RECEIVER
The HDMI receiver on the ADV7441A incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cables, especially those with long lengths and high frequencies. It is capable of equalizing for cable lengths up to 30 meters and, therefore, can achieve robust receiver performance at even the highest HDMI data rates. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7441A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol.
Rev. B | Page 16 of 28
ADV7441A
COMPONENT PROCESSOR (CP)
The component processor section is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The CP section of the ADV7441A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. If no embedded synchronization is present, the video gain can be set manually. A fully programmable any-to-any 3 x 3 color-space converter is placed before the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color-space converter. A second fully programmable any-to-any 3 x 3 color space converter is placed in the back end of the CP core. This color space converter features advanced color controls such as contrast, saturation, brightness, and hue controls. The output section of the CP is highly flexible. It can be configured in single data rate mode (SDR) with one data packet per clock cycle. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In these modes, HS/CS, VS/FIELD, and DE/FIELD (where applicable) timing reference signals are provided. The CP section contains circuitry to enable the detection of Macrovision-encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals.
VBI DATA PROCESSOR
VBI extraction of CGMS data is performed by the VBI data processor (VDP) section of the AD7441A for interlaced, progressive, and high definition scanning rates. The data extracted is read back over the I2C interface. For more detailed product information about the ADV7441A, send an e-mail to video.products@analog.com or contact a local Analog Devices sales representative.
Rev. B | Page 17 of 28
ADV7441A PIXEL OUTPUT FORMATTING
Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Standard Definition Pixel Port Modes (P19 to P0)
Processor SDP SDP SDP SDP SDP SDP Mode/Format Mode 1 Video output 8-bit 4:2:2 Mode 2 Video output 10-bit 4:2:2 Mode 3 Video output 16-bit 4:2:2 Mode 4 Video output 20-bit 4:2:2 Mode 5 Video output 24-bit 4:4:4 Mode 6 Video output 30-bit 4:4:4 19 18 17 16 15 14 YCrCb[7:0] YCrCb[9:0] Y[7:0] Y[9:0] Y[7:0] Y[9:0]
- - - -
13
Data Port Pins P[19:0] 12 11 10 9 8
- - - - - -
7
- -
6
- -
5
- -
4
- -
3
- -
2
- -
1
- - -
0
- - -
CrCb[7:0] Cb[9:0] Cb[7:0] Cb[9:0]
-
-
Table 9. Standard Definition Pixel Port Modes (P29 to P20)
Processor SDP SDP SDP SDP SDP SDP Mode/Format Mode 1 Video output 8-bit 4:2:2 Mode 2 Video output 10-bit 4:2:2 Mode 3 Video output 16-bit 4:2:2 Mode 4 Video output 20-bit 4:2:2 Mode 5 Video output 24-bit 4:4:4 Mode 6 Video output 30-bit 4:4:4 29
- - - -
28
- - - -
27
- - - -
Data Port Pins P[29:20] 26 25 24 23
- - - - - - - - - - - - - - - -
22
- - - -
21
- - - - -
20
- - - - -
Cr[7:0] Cr[9:0]
Rev. B | Page 18 of 28
ADV7441A
Table 10. Component Processor Pixel Output Pin Map (P19 to P0)
Processor 1 CP Mode/Format Mode 1 Video output 8-bit 4:2:2 2 Mode 2 Video output 10-bit 4:2:22 Mode 3 Video output 12-bit 4:2:22 Mode 4 Video output 12-bit 4:2:22 Mode 5 Video output 12-bit 4:2:22 Mode 6 Video output 16-bit 4:2:2 3, 4 Mode 7 Video output 20-bit 4:2:23, 4 Mode 8 Video output 20-bit 4:2:223, 4 Mode 9 Video output 24-bit 4:2:23, 4 Mode 10 Video output 24-bit 4:2:23, 4 Mode 11 Video output 24-bit 4:2:23, 4 Mode 12 Video output 24-bit 4:4:43, 4 Mode 13 Video output 24-bit 4:4:43, 4 Mode 14 Video output 24-bit 4:4:43, 4 Mode 15 Video output 24-bit 4:4:43, 4 Mode 16 Video output 30-bit 4:4:43, 4 19 18 17 16 15 14 YCrCb[7:0] Output of Data Port Pins P[19:0] 13 12 11 10 9 8 7 6
- - - - - -
5
-
4
-
3
-
2
-
1
-
0
-
CP
YCrCb[9:0]
-
-
-
-
-
-
-
-
-
-
CP
YCrCb[11:2]
-
-
-
-
-
-
-
-
-
-
CP
YCrCb[11:4]
-
-
-
-
-
-
-
-
-
-
-
-
CP
YCrCb[11:4]
-
-
YCrCb[3:0]
-
-
-
-
-
-
CP
CHA[7:0] (default data is Y[7:0])
-
-
CHB/CHC[7:0] (default data is Cr/Cb[7:0])
-
-
CP
CHA[9:0] (default data is Y[9:0])
CHB/CHC[9:0] (default data is Cr/Cb[9:0])
CP
CHA[9:2] (default data is Y[9:2])
-
-
CHB/CHC[9:2] (default data is Cr/Cb[9:2])
-
-
CP
Y[11:2]
CrCb[11:2]
CP
Y[11:4]
-
-
CrCb[11:4]
-
-
CP
Y[11:4]
-
-
Y[3:0]
CrCb[3:0]
-
-
CP
CHA[7:0] (default data is G[7:0] or Y[7:0])
-
-
CHB[7:0] (default data is R[7:0] or Cr[7:0])
-
-
CP
CHA[7:0] (default data is G[7:0] or Y[7:0])
-
-
CHC[7:0] (default data is B[7:0] or Cb[7:0]) CHA[7:0] (default data is G[7:0] or Y[7:0])
-
-
CP
CHC[7:0] (default data is B[7:0] or Cb[7:0])
-
-
-
-
CP
CHC[7:0] (default data is B[7:0] or Cb[7:0])
-
-
CHB[7:0] (default data is R[7:0] or Cr[7:0])
-
-
CP
CHA[9:0] (default data is G[9:0] or Y[9:0])
CHB[9:0] (default data is R[9:0] or Cr[9:0])
Rev. B | Page 19 of 28
ADV7441A
Processor 1 CP Mode/Format Mode 17 Video output 30-bit 4:4:43, 4 Mode 18 Video output 30-bit 4:4:43, 4 Mode 19 Video output 30-bit 4:2:23, 4 19 Output of Data Port Pins P[19:0] 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CHA[9:0] (default data is G[9:0] or Y[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0]) 0
CP
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHA[9:0] (default data is G[9:0] or Y[9:0])
CP
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHB[9:0] (default data is R[9:0] or Cr[9:0])
1 2
CP processor uses digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz (analog digitizer). 4 Maximum pixel clock rate of 165 MHz (HDMI).
Table 11. Component Processor Pixel Output Pin Map (P29 to P20)
Processor 1 CP Mode/Format Mode 1 Video output 8-bit 4:2:2 2 Mode 2 Video output 10-bit 4:2:22 Mode 3 Video output 12-bit 4:2:22 Mode 4 Video output 12-bit 4:2:22 Mode 5 Video output 12-bit 4:2:22 Mode 6 Video output 16-bit 4:2:2 3, 4 Mode 7 Video output 20-bit 4:2:23, 4 Mode 8 Video output 20-bit 4:2:23, 4 Mode 9 Video output 24-bit 4:2:23, 4 Mode 10 Video output 24-bit 4:2:23, 4 Mode 11 Video output 24-bit 4:2:23, 4 Mode 12 Video output 24-bit 4:4:43, 4 29
-
28
-
27
-
Output of Data Port Pins P[29:20] 26 25 24 23
- - - -
22
-
21
-
20
-
CP
-
-
-
-
-
-
-
-
-
-
CP
-
-
-
-
-
-
YCrCb[1:0]
-
-
CP
-
-
-
-
YCrCb[3:0]
-
-
CP
-
-
-
-
-
-
-
-
-
-
CP
-
-
-
-
-
-
-
-
-
-
CP
-
-
-
-
-
-
-
-
-
-
CP
Y[1:0]
CrCb[1:0]
-
-
-
-
-
-
CP
-
-
CrCb[1:0]
-
-
Y[1:0]
-
-
CP
CrCb[3:0]
Y[3:0]
-
-
CP
CrCb[11:4]
-
-
CP
CHC[7:0] (for example, B[7:0] or Cb[7:0])
-
-
Rev. B | Page 20 of 28
ADV7441A
Processor 1 CP Mode/Format Mode 13 Video output 24-bit 4:4:43, 4 Mode 14 Video output 24-bit 4:4:43, 4 Mode 15 Video output 24-bit 4:4:43, 4 Mode 16 Video output 30-bit 4:4:43, 4 Mode 17 Video output 30-bit 4:4:43, 4 Mode 18 Video output 30-bit 4:4:43, 4 Mode 19 Video output 30-bit 4:2:23, 4 29 28 Output of Data Port Pins P[29:20] 27 26 25 24 23 CHB[7:0] (for example, R[7:0] or Cr[7:0]) 22 21
-
20
-
CP
CHB[7:0] (for example, R[7:0] or Cr[7:0])
-
-
CP
CHA[7:0] (for example, G[7:0] or Y[7:0])
-
-
CP
CHC[9:0] (for example, B[9:0] or Cb[9:0])
CP
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CP
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CP
CHA[9:0] (for example, G[9:0] or Y[9:0])
1 2 3
CP processor uses digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. Maximum pixel clock rate of 170 MHz (analog digitizer). 4 Maximum pixel clock rate of 165 MHz (HDMI).
Rev. B | Page 21 of 28
ADV7441A
REGISTER MAP ARCHITECTURE
The ADV7441A registers are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7441A has eight maps, each with a unique I2C address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Table 12. Table 12. Register Map Addresses
Register Map User Map User Map 1 User Map 2 VDP Map Reserved Map HDMI Map Repeater KSV Map EDID Map Default Address with ALSB = Low 0x40 0x44 0x60 0x48 0x4C 0x68 0x64 0x6C Default Address with ALSB = High 0x42 0x46 0x62 0x4A 0x4E 0x6A 0x66 0x6E Programmable Address Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Location Where Address Can Be Programmed N/A User Map 2, Register 0xEB User Map, Register 0x0E User Map 2, Register 0xEC User Map 2, Register 0xEA User Map 2, Register 0xEF User Map 2, Register 0xED User Map 2, Register 0xEE
USER MAP
USER MAP 1
USER MAP 2
VDP MAP
SA: 0x40
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SCL SDA
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
HDMI MAP
EDID MAP
Figure 7. Register Map Access Through Main I2C Port
Rev. B | Page 22 of 28
06914-008
REPEATER KSV MAP
RESERVED MAP
ADV7441A TYPICAL CONNECTION DIAGRAM
Figure 8. Typical Connection Diagram
Rev. B | Page 23 of 28
06914-009
ADV7441A
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10.
ELPF 70 1.69k 10nF
AUDIO_ELPF 102 1.5k 8nF
82nF
80nF
PVDD = 1.8V
Figure 9. ELPF Components
Figure 10. AUDIO_ELPF Components
Rev. B | Page 24 of 28
06914-011
PVDD = 1.8V
06914-010
ADV7441A AD9388A/ADV7441A EVALUATION PLATFORM
Analog Devices has developed a new evaluation platform for the AD9388A/ADV7441A decoders. The evaluation platform consists of a motherboard and two daughterboards. The motherboard features a Xilinx FPGA for digital processing and muxing functions. The motherboard also features three AD9742s (12-bit DACs) from Analog Devices. This allows the user to drive a VGA monitor with just the motherboard and front-end board. The backend of the platform can be connected to a specially developed video output board from Analog Devices. This modular board features an ADV7341 encoder and AD9889B HDMI transmitter. The front end of the platform consists of an EVALAD9388AFEZ_x or EVAL-ADV7441AFEZ_x board. This board feeds the digital outputs from the decoder to the FPGA on the motherboard. The EVAL-AD9388AFEZ_x or EVALADV7441AFEZ_x board comes with one of the pin-compatible decoders shown in Table 13.
Table 13. Front-End Modular Board Details
Front-End Modular Board Model
EVAL-ADV7441AFEZ_1 EVAL-ADV7441AFEZ_2 EVAL-AD9388AFEZ_1 EVAL-AD9388AFEZ_2 EVAL-AD9388AFEZ_3
On-Board Decoder ADV7441ABSTZ-170 ADV7441ABSTZ-5P AD9388ABSTZ-170 AD9388ABSTZ-5P AD9388ABSTZ-A5
HDCP License Required Yes No Yes No Yes
AUDIO 96-PIN CONNECTOR
ATV MOTHERBOARD VIDEO INPUT BOARD EVAL-AD9388AFEZ_x OR ADV7441AFEZ_x
AVI 168-PIN CONNECTOR AD9388A/ADV7441A DECODER
Xilinx FPGA
VGA OUTPUT
ANALOG AND DIGITAL VIDEO INPUTS AVO 168-PIN CONNECTOR
VIDEO OUTPUT BOARD
CVBS
AD9889B
ADV7341
Y/C
HDMI
YPrPb
Figure 11. Functional Block Diagram of Evaluation Platform
Rev. B | Page 25 of 28
06914-012
ADV7441A OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
144 1 PIN 1
22.20 22.00 SQ 21.80
109 108
TOP VIEW
(PINS DOWN)
20.20 20.00 SQ 19.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0
36 37 72
73
0.08 COPLANARITY
VIEW A
ROTATED 90 CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BFB
Figure 12. 144-Lead Low Profile Quad Flat Package [LQFP] (ST-144) Dimensions shown in millimeters
ORDERING GUIDE
Model ADV7441ABSTZ-170 1, 2 ADV7441ABSTZ-1101, 2 ADV7441ABSTZ-5P1, 3, 4 EVAL- ADV7441AFEZ_1 1, 2, 5 EVAL- ADV7441AFEZ_21, 4, 6
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] Front End Evaluation Board Front End Evaluation Board
Package Option ST-144 ST-144 ST-144
Z = RoHS Compliant Part. This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC for licensing requirements) to purchase any components with internal HDCP keys. 3 Speed grade: 5 = 170MHz. HDCP functionality: P = no HDCP functionality (pro version). 4 Professional version for nonHDCP encrypted applications. Purchaser is not required to be a HDCP adopter. 5 Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-170 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on evaluation platform. 6 Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-5P decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on evaluation platform.
Rev. B | Page 26 of 28
ADV7441A NOTES
Rev. B | Page 27 of 28
ADV7441A NOTES
(c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06914-0-7/08(B)
Rev. B | Page 28 of 28

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